Referring now to FIG. 1, a network device 10 is shown that includes a central processing unit (CPU) 12 and low latency and high latency memories 14 and 16. An interface controller 20 communicates with the low latency and high latency memories 14 and 16 via buses 22 and 24, respectively. The interface controller 20 communicates with the CPU 12 via bus 26. A network adaptor 32 communicates with the interface controller 20 via a bus 34. The CPU 12 processes data and communicates with the low latency memory 14, the high latency memory 16, and/or the bus 34 through the interface controller 20. The network adaptor 32 facilitates communications between a network 40 and the CPU 12 via the bus 34.
In the network device 10, the low latency memory 14 generally has higher performance than the high latency memory 16. For example, the low latency memory 14 can be static random access memory (SRAM), which has relatively fast read/write access times and a relatively high cost. The low latency memory 14 can be embedded or external. The high latency memory 16 has slower read/write access times and is typically less expensive than the low latency memory. For example, the high latency memory 16 can be dynamic random access memory (DRAM).
Due to the cost difference, the memory capacity of the low latency memory 14 is usually substantially lower than the memory capacity of the high latency memory 16. In other words, while it is desirable to have as much of the low latency memory 14 as possible to improve performance, the cost of the low latency memory 14 usually requires a trade-off between system cost and performance. Usually, substantially more of the high latency memory 16 is used due to its lower cost. In addition, the smaller physical size of the low latency memory 14 allows it to be located near the interface controller 20 or embedded on the same chip as the interface controller 20. The proximity of the low latency memory 14 further improves data access times.
Referring now to FIG. 2, in networking applications, data is typically communicated in data packets 44 that include a header portion 46 and a data portion 48. The header portion 46 includes instructions, such as routing, protocol and other information, for the data portion 48.
When the CPU and/or the network adaptor 32 read from or write to the high latency memory 16, the interface controller 20 uses two conventional approaches. In a first approach, a base address and a buffer pool size are specified by a descriptor control structure and are stored in registers of the interface controller 20. In a second approach, a base address register and mask are specified by the descriptor control structure and are stored in registers of the interface controller.
The values stored in the base address register and the buffer pool size or mask register are used by the CPU 12 and the interface controller 20 when storing and retrieving the packets from the high latency memory 16. The descriptor control structure is prepared by the driver software that runs the CPU 12. The descriptor control structure is used by the hardware-based direct memory access (DMA) engine to read/write data packets to/from the high latency memory 16.
In FIG. 3, registers 49 of the interface controller 20 for the first approach are shown. The registers 49 include a base address register 50, a buffer pool size register 52, and/or other optional descriptor registers 54 (if any). In FIG. 4, registers 49′ of the interface controller 20 for the second approach are shown. The registers 49′ include a base address register 50, a mask register 58, and/or other optional descriptor registers 60 (if any).
The network adaptor 32 receives instructions from the CPU 12 based on the registers 49 or 49′. The CPU 12 instructs the network adaptor 32 where to write the data packets in the high latency memory. The data packets 44 are sent from the network 40 through the network adaptor 32 to the network device 10. The data packets 44 are then stored in the high latency memory 16 based on the instructions from the CPU 12.
The low latency memory 14 is not used for the data packets 44 due to the large size of the data packets 44 and the relatively-low capacity of the low latency memory 14. Reading and writing access times that are required by the CPU 12 are adversely impacted by the relatively low data read/write speeds of the high latency memory 16.